With emergence of integration technologies, such as Through-Silicon-Via (TSV), to combine passive components with the active component circuits, high density trench (or “hole”) capacitors have begun to replace discrete storage capacitors in order to meet the scaling demands of smaller hand-held circuit designs.
A basic trench capacitor is a small three-dimensional device formed by etching a trench into a semiconductor substrate. After trench etching, a doped region may be formed in the lower portion around and below the trench, which serves as an outer electrode or a buried plate electrode of a trench capacitor. A dielectric layer may be formed over the outer or buried plate electrode in the trench. The dielectric layer serves as an insulating layer between the electrodes of the trench capacitor. This is followed by filling the trench, for example, with conductive polycrystalline silicon (herein after poly-Si), which serves as an inner or upper electrode of the trench capacitor. It has become more common to create silicon devices having closely-packed arrays of deep trench capacitors. The deep trenches may have extremely high aspect-ratios (ranging from about 20:1 to about 120:1). The extremely high trench aspect ratios are used to help increase the capacitance density of, for example, double MIM capacitors. The creation of closely-packed arrays of deep trenches increases the top side silicon wafer surface area to be equivalent to that of the area of up to about 50 top side surface-wafers. Furthermore, a double MIM capacitor requires a minimum of six layers. Three layers for the first MIM capacitor (e.g., TiN/Hi-k/TiN) and three additional substantially similar layers for the second MIM capacitor. All of the layers of a MIM capacitor induce tensile stress on the top side or upper surface of the silicon wafer, which with high trench densities causes a silicon wafer to warp or bow upwards.
FIG. 1 is meant to depict a cross sectional view of a silicon wafer comprising closely packed arrays of deep trenches, each having high aspect-ratios, on the wafer's top surface. The combination of the double MIM capacitor layers and the increased surface area on the top side of the wafer causes a wafer to bow upward in a convex manner. Wafer bowing can be up to about two hundred (200) micrometers (um). Wafer bowing impacts the downstream wafer manufacturing process by affecting photo-alignment processes and subjecting the wafers to a higher than normal breakage rate in various stages of wafer fabrication processing and assembly. Furthermore, it has been found that high convex wafer bowing may be increased (for example by an additional 150 micrometers of bow), if an in-situ doped (ISD) poly-Si film or layer is used in a manufacturing process to fill the trenches and interconnect the double MIM capacitors created in the deep trenches. It is well known that ISD poly-Si film may be formed by depositing an amorphous silicon (a-Si) t incorporate enough dopants and annealing the a-Si into poly-Si to activate the dopant. And, it is the anneal that adds additional tensile stress to the top side of a silicon wafer when applied thereon.
The high convex wafer bowing or wafer warpage causes problems during the various manufacturing and assembly steps of a wafer. For example, during a wafer chemical mechanical polishing (CMP) or a grinding process, a warped wafer is more apt toward breakage. Also, when a wafer is warped or not flat, depth measurements for alignments and placements of contact landing pads and their associated contacts are affected. Finally, warpage causes the silicon chip yields to be low, sometimes as low as 10 to 15 percent, due to the above discussed errors and problems encountered during the manufacturing process.
What is needed is a single, double or triple MIM capacitor construction that can be produced in closely-packed, high-density arrays of deep trenches on a top surface of a silicon wafer, which does not cause or counter warpage caused by the tensile stressed layers of material used to produce the single or multi layered deep trench capacitors.